Smc-networks ARM PL241 Instrukcja Użytkownika Pobierz pdf (Strona 83)

Programmer’s Model

The following sections describe the smc_pcell_id Registers:

• SMC PrimeCell Identification Register 0

• SMC PrimeCell Identification Register 1

• SMC PrimeCell Identification Register 2 on page 3-24

• SMC PrimeCell Identification Register 3 on page 3-24.

Note

These registers cannot be read in the Reset state.

SMC PrimeCell Identification Register 0

The smc_pcell_id_0 Register is hard-coded and the fields within the register indicate

the value. Table 3-20 lists the register bit assignments.

SMC PrimeCell Identification Register 1

The smc_pcell_id_1 Register is hard-coded and the fields within the register indicate

the value. Table 3-21 lists the register bit assignments.

Table 3-20 smc_pcell_id_0 Register bit assignments

Bits Name Function

[31:8] - Reserved, read undefined

[7:0] smc_pcell_id_0 These bits read back as

0x0D

Table 3-21 smc_pcell_id_1 Register bit assignments

Bits Name Function

[31:8] - Reserved, read undefined

[7:0] smc_pcell_id_1 These bits read back as

0xF0

1 2 ... 78 79 80 81 82 83 84 85 86 87 88 ... 109 110

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Smc-networks ARM PL241 Instrukcja Użytkownika Strona 83