Smc-networks ARM PL241 Instrukcja Użytkownika Pobierz pdf (Strona 80)

Programmer’s Model

Figure 3-18 shows the correspondence between bits of the smc_ periph_id registers and

the conceptual 32-bit Peripheral ID Register.

Figure 3-18 smc_periph_id Register bit assignments

The following section describe the smc_periph_id Registers

• SMC Peripheral Identification Register 0

• SMC Peripheral Identification Register 1 on page 3-21

• SMC Peripheral Identification Register 2 on page 3-21

• SMC Peripheral Identification Register 3 on page 3-21.

SMC Peripheral Identification Register 0

The smc_periph_id_0 Register is hard-coded and the fields within the register indicate

the value. Table 3-15 lists the register bit assignments.

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8QGHILQHG

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UHYLVLRQ

 

GHVLJQHUB

GHVLJQHUB

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GHVLJQHU



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SDUWBQXPEHU

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SDUWBQXPEHUB

SDUWBQXPEHUB



$FWXDOUHJLVWHUELWDVVLJQPHQW

&RQFHSWXDOUHJLVWHUELWDVVLJQPHQW

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LQWHJUDWLRQBFIJ

Table 3-15 smc_periph_id_0 Register bit assignments

Bits Name Function

[31:8] - Reserved, read undefined

[7:0] part_number_0 These bits read back as

0x52

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 ... 109 110

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Smc-networks ARM PL241 Instrukcja Użytkownika Strona 80